1. Field of the Invention
The present invention relates to a storage device and an image data processing apparatus.
2. Description of the Related Art
Computer graphics are often used in a variety of computer aided design (CAD) systems and amusement machines. Especially, along with the recent advances in image processing techniques, systems using three-dimensional computer graphics are becoming rapidly widespread.
In three-dimensional computer graphics, the color value of each pixel is calculated at the time of deciding the color of each corresponding pixel. Then, rendering is performed for writing the calculated value to an address of a display buffer (frame buffer) corresponding to the pixel.
One of the rendering methods is polygon rendering. In this method, a three-dimensional model is expressed as an composite of triangular unit graphics (polygons). By drawing the polygons as units, the colors of the pixels of the display screen are decided.
In polygon rendering, coordinates (x, y, z), color data (R, G, B), homogeneous coordinates (s, t) of texture data indicating a composite image pattern, and a value of the homogeneous term q for the respective vertexes of the triangle in a physical coordinate system are input and processing is performed for interpolation of these values inside the triangle.
Here, the homogeneous term q is, simply stated, like an expansion or reduction rate. Coordinates in a UV coordinate system of an actual texture buffer, namely, texture coordinate data (u, v), are comprised of the homogeneous coordinates (s, t) divided by the homogeneous term q to give xe2x80x9cs/qxe2x80x9d and xe2x80x9ct/qxe2x80x9d which in turn are multiplied by texture sizes USIZE and VSIZE, respectively.
FIG. 28 is a view of the system configuration of the basic concept of a three-dimensional computer graphics system.
In the three-dimensional computer graphics system, data for drawing graphics etc. is given from a main memory 2 of a main processor 1 or an I/O interface circuit 3 for receiving graphic data from outside to a rendering circuit 5 having a rendering processor 5a and a frame buffer memory 5b via a main bus 4.
The rendering processor 5a is connected to a frame buffer 5b for holding data to be displayed and a texture memory 6 for holding texture data to be applied on a surface of a graphic element (for example, a triangle) to be drawn.
Then, the rendering processor 5a performs processing to draw to the frame buffer 5b the graphic element being given a texture on its surface for every element.
The frame buffer 5b and the texture memory 6 are generally composed of a dynamic random access memory (DRAM).
Between the frame buffer 5b and texture memory 6 and the main processor is usually provided a first-in first-out (FIFO) circuit.
In the related art, when outputting data read for example from the frame buffer 5b and the texture memory 6 to the main processor 1 via the FIFO circuit, a controller monitors an empty region of the FIFO circuit. When the amount of the empty region becomes a predetermined value or more, a read request is continuously output to the frame buffer memory 5b and the texture memory 6 until the empty region is used up.
When image data including a plurality of pixel data is read from the frame buffer 5b or the texture memory 6 into the main processor 1 by a read request, if only continuously outputting the read request until the empty region is used up as explained above, there arises a situation that a part of the image data included in the read image data in accordance with the last read request is not written in the FIFO circuit due to insufficient empty space.
In such a case, it is necessary that the controller read the same image data as the previous time one more time when the amount of the empty region of the FIFO circuit becomes a predetermined value or more next, specify the image data not written in the FIFO circuit at the previous time in the read image data, and perform control to write only the specified image data into the FIFO circuit. Therefore, there are the disadvantages that the control by the controller becomes complicated and the load of the controller becomes larger.
An object of the present invention is to provide a storage device and an image data processing apparatus enabling input control of the FIFO circuit simply.
According to a first aspect of the present invention, there is provided a storage device comprising a data output circuit for outputting a data having a data length indicated by one read indication signal among a plurality of read indication signals giving different data lengths of data output, in response to one read output request; a memory circuit for receiving and storing the data output from the data output circuit; and a control circuit for outputting the output request by a number of times in response to the data length indicated by the read indication signal to the data output circuit when a predetermined amount of an empty region is generated in said memory circuit.
Preferably, the control circuit outputs the output request by a number of times in response to the data length indicated by the read indication signal to the data output circuit so that all of the data output from the data output circuit to the memory circuit by the output request is written in the entire region of the empty region.
Preferably, the memory circuit comprises a first-in first-out (FIFO) circuit.
Preferably, the control circuit outputs the output request for a number of times in response to the data length indicated by the read indication signal to the data output circuit when half of a memory region in the memory circuit becomes empty.
According to a second aspect of the present invention, there is provided an image data processing apparatus, comprising a first memory circuit capable of storing a plurality of image data having different data lengths of valid pixel data, output in accordance with one read request; a second memory circuit for receiving and storing the valid pixel data output from the first memory circuit; and a control circuit for outputting the read request by a number of times in accordance with the data length to the first memory circuit when a predetermined amount of an empty region is generated in the second memory circuit.
Preferably, the control circuit outputs the read request for a number of times in accordance with the data length to the first memory circuit so that all of the pixel data output from the first memory circuit to the second memory circuit by the read request is written in the entire region of the empty region in the second memory circuit.
Preferably, it further comprises an image processing circuit for performing image processing based on pixel data read from the second memory circuit.
Preferably, it further comprises a rearrangement circuit for rearranging image data including pixel data read from the second memory circuit in pixel data units and generating image data for being input to the image processing circuit when a data length of the image data read from the first memory means and a data length of image data including the pixel data to be input to the image processing circuit are different.
Preferably, the first memory circuit comprises an FIFO circuit.
According to a third aspect of the present invention, there is an image data processing circuit for performing rendering processing by using polygon rendering data including three-dimensional coordinates (x, y, z), R(red), G(green) and B(blue) data, texture homogenous coordinates (s, t), and a homogeneous term q with respect to vertexes of a unit graphic, comprising a first memory circuit for storing display data, and texture data required by at least one graphic element and defined a data amount of valid pixel data read by one read request; a second memory circuit for receiving and storing the valid pixel data read from the first memory circuit; an interpolation data generation circuit for interpolating polygon rendering data of vertexes of the unit graphic and generating interpolating data of pixels positioned inside the unit graphic; a texture processing circuit for generating xe2x80x9cs/qxe2x80x9d and xe2x80x9ct/qxe2x80x9d by dividing the texture homogeneous coordinates (s, t) included in the interpolation data by the homogeneous term q and generating display data by performing applying the texture data read from the first memory circuit on the surface of graphic elements by using a texture address in response to the xe2x80x9cs/qxe2x80x9d and xe2x80x9ct/qxe2x80x9d; a control circuit for outputting the read request by a number of times in accordance with the data amount to the first memory circuit when a predetermined amount of an empty region is generated in the second memory circuit; and an interface circuit for outputting pixel data read from the second memory circuit.
Preferably, the control circuit outputs the read request by a number of times in accordance with the data amount to the first memory circuit so that all of the pixel data output from the first memory circuit to the second memory circuit by the read request is written in the entire region of the empty region.
Preferably, it further comprises a data rearrangement circuit for rearranging the pixel data input from the second memory circuit in accordance with a signal processing mode of the interface circuit and outputting the rearranged pixel data to the interface circuit.
Preferably, the first memory circuit comprises an FIFO circuit.
Preferably, the second memory circuit comprises a DRAM.